Circuit arrangement for high speed distance relaying



Dec. 29, 1964 Filed May 9, 1962 L. SEGUIN ETAL CIRCUIT ARRANGEMENT FOR HIGH SPEED DISTANCE RELAYING 3 call/Mum urfzoM ci 4 Sheets-Sheet 1 Jiuazajars.

54,6 9 Jqfi Dec. 29, 1964 L. SEGUIN ETAL CIRCUIT ARRANGEMENT FOR HIGH SPEED DISTANCE RELAYING Filed May 9, 1962 4 Sheets-Sheet 2 ja fe fw' g Dec. 29, 1964 L. SEGUIN ETAL 3,163,302

CIRCUIT ARRANGEMENT FOR HIGH SPEED DISTANCE RELAYING Filed May 9, 1962 4 Sheets-Sheet 4 United States Patent Cfilice 3,153,802 Patented Dec. 29, 1964 The invention disclosed herein is concerned with a high speed distance relaying arrangement for protecting power systems in the caseof faults, for example, a short circuit on a line section.

Nearly all presently employed relay systems for pro tecting power lines contain mechanical systems performing electrical control or measuring operations. inertia, such systems respond to average values of the current conducted thereto. Increasingly higher requirements are being posed on protection systems and devices so far as the speed of operation and current consumption thereof are concerned, leading toward endeavors to re,

duce the inertia of the mechanical control members. So far as the principle is concerned, it would be possible to reduce the inertia so as to obtain operative response of the control system in a split cycle of the line current. However, such speed of operation cannot be utilized in connection with any presently known distance relay, since the forces, operating on the mechanical members, particularly when a fault current contains a direct current component, can pulsate respectively with the same or twice the frequency of the current. In order to prevent incorrect operation due to these pulsating forces, the control system must be made to operate with inertia, so great that it responds operatively only to an average value of the force applied. Accordingly, the lower time limit of protection devices operating with mechanical measuring systems can hardly go lower than one cycle.

In order to break through this barrier and to reduce at the same time the load of the measuring transformers by the protective relays, attempts have for a long time been made to construct distance protection devices with the aid of electronic means. These attempts gain increasing importance owing to therapid progress made in the development of semiconductors.

The basic difference between electronic protective systems and those operating with mechanical control members resides in that the former inherently operate in response to momentary electrical values conducted thereto, while the latter, as explained above, always respond to an average value. This situation explains a few peculiarities which must be observed in connection with an electronic protection, especially the sensitivity with respect to short interference impulses. q

The proposals heretofore made, for electronic protective systems, can be subdivided into two groups. The feature which is common to both groups is, that the line voltage u and the voltage a at a comparison impedance, which is energized by the line current, must be brought into mutual relationship. I a i 1 In the case of one group of previously proposed systems, the polarity of the voltage u and the di ference u -u of the two voltages are compared, and a signal for Owing to by the current course or the voltage course, such systems being referred to as momentary or instantaneous value protection.

In each group of systems are in this manner obtained different utilizable operating characteristic in the impedance (R-X) diagram. However, the corresponding systems have disadvantages which until now stood against practical application thereof. Among these disadvantages may be noted the following peculiarities: The mode of operation of the devices was always derived for purely sinusoidal values, especially also for a sinusoidal current which is due to a fault on the line to be protected. However, in the case of rapidly operating devices, which are to operate selectively within the first half wave of a faultcurrent, there must be considered the direct current component of the fault current. This leadsin systems of the first noted group to a considerable broadening of the operating characteristic. Further difficulties are occasioned upon considering the resistance resulting from the possible formation of an arc. Systems in the second group of proposals are extraordinarily sensitive to interference pulses occurring at the instant of measurin Moreover, the peculiarities of the arc may in such case likewise cause difficulties, especially in a system inwhich the current is fed from two sides.

The object of the present invention is to provide a new measuring or control system which avoids the disadvantages of the previously known selective electronic protection devices. The invention provides a high speed protective relaying arrangement to which are conducted, for the formation of an operation criterion, the line voltage 1: and the voltage n at the comparison impedance, and in which is formed the diiterence voltage Au=u u, the characteristic feature of the invention residing in that the polarities of the named voltages, orvalues derived therefrom, are in each current halt wave evaluated only within a time interval 41 during which interval the fault current i and its temporal derivation di/dt have the same sign.

The invention will now be explained more in detail with reference to the accompanying drawings.

FIG. l'shows in schematic representation a single-phase line with current supply at both ends thereof;

FIG, 2 taken together with FIG. 1 explains the importance which is attached to limiting the evaluation to a time interval in which i and di/a t have the same sign; and

FIGS. 3, Sand 7 show the operating characteristics resulting in the embodiments which are respectively represented in FIGS. 4, 6 and 8.

The circuits shown in FIGS. 4, 6 and 8 are constructed along the principles of the digital controland regulafollowing explanations take into consideration the protection provided in the substation 3 which isto protect the line up to the substation 4-. It is assumed that a fault occurs along this line section. The resistance of this fault shall be neglected for the general observations to be entered into. The impedance between the location of the fault and the substation 3 is in such situation given by the line impedance comprising the ohmic component R and the inductive component wL. The fault current i passes through this impedance and produces in the substation 3 the line voltage u. The fault current i also flows througha comparison impedance R wL which is normally connected to the secondary side of the current transformers. Upon assuming that the voltage at this comparison impedance amounts to u there will be between the momentary or instantaneous values of the voltages u and u and-the current i, the following relations:

Upon subtracting Equation 1 from the Equation 2, there Based upon the Equations 1 and 3, which are entirely independent of the curve form of the fault current, and assuming that i and di/dt havethe same. sign or, more descriptively expressed,- that they are in the region between zero passage and the maximumofthe fault current, there may be made the following statements, whereby references to polarity and sign point to the indicia arrows entered in FIG. 1:

(1) For R 0 and L the voltage u must have the same sign as i and di/dt (Equation 1).

('2) For R O and L 0, the voltage u must have a sign opposite to that of i anddi/dt (Equation 1).

(3) For R R (R -R- O) and L L (L L 0), the voltage Au must have the same sign as i and di/dt (Equation 3). Y

(4) For R R (R -R- 0) and L L (L -L 0)', the voltage Au must have a sign opposite to that ofi and di/dt (Equation 3).

It is, based upon these statements possible to distinguish in an impedance diagram such as shown in FIG. 2, wherein Z, (R wL is the comparison impedance, with certainty three regions:

Region a: R R 0 L L 0. The voltage u always has the same sign as i and di/dt, while the voltage Au always has a sign opposite to thatofiand di/dt.

Region h: R R O L L. 0. The voltages u and Au always have the same sign as i and di/dt.

Regionc: R 0 L 0. The voltageAu always has the same sign as i and di/dt and the voltage u always has a sign opposite to that of i and di/dt.

It is accordingly possible, by comparison, within the evaluation interval, of the polarity of the two voltages u and Au withthat of i and di/dz, to delimit three regions in the impedance. diagram independent of the'curve form of the current. Proper selection of the comparison impedance Z as contrasted with the impedance of the line section which is to be protected, will make it possible that the relay arrangement is to operate always in the presence of line impedances' in the region b and never to operate in the presence of line impedances in the regions a and c. 7

It is now possible, with observance of the characteristic feature of the invention according to which meas urements are effected only when i and di/dt have the same sign, to determine with the aid of the voltages u and Au various operation criteria. Three embodiments will be described below togive examples of the use of such criteria.

Depending upon the accurate determination of the operation criterion, an operation area will be delimited in the impedance diagram, which always contains the region b of FIG. 2 and the borders or limits of which lie in the unhatched region of FIG. 2. However, this delimiting depends more or less upon curve form of the current. In order to take this influence into consideration, there shall be assumed a current course according to the following Equation 4:

i=l.(sin (wt-(p +sin (4) The fault isassumed to appear at the time i=0; the transient offset of the fault current is given by the angle a,; the damping of the transient offset component in the fault current shall be neglected. It is moreover for simplification assumed that the evaluation time t embraces the entire interval from current zero passage to the current maximum.

As explained previously, the influence of interference pulses must be particularly considered in connection with all electronic protection systems. The safest'way to eliminate the detrimental influence of' interference pulses resides in integrating the electrical values effected thereby.

Accordingly, in a first example of a high speed protective relaying arrangement embodyingthe features of the invention, an operation command or signal is given to the involved circuit breaker, when the time integral: of the voltage u as well as that of the difference voltage Au have at the end of the evaluation interval t the same polarity as the fault current i, whereby-the duration of integration extends over theentire evaluation time interval 1 Upon fulfilling this operation requirement, the voltage u as well as the difference voltage Au Will,- during the evaluation interval' t have preponderantly the same polarity as i and di/dt. It can be demonstrated, uponassuming a current course according to Equation 4, that the borders of the operation region become two straight line flights extending respectively through the origin and the end point of the vector Z whereby the inclination of the straight lines depends upon the angle (p and therewith upon the amount of current offset. FIG; 3 shows these straight linesfor difierent angles (p the respective operation regions always lying. between parallel straight lines for the corresponding angle, extending respectively through the points of origin and endof thevectorZ FIG. 4 shows an example of an embodiment of the invention. Numerals-11 and 12 indicatenull amplifiers, in the regulation art sometimes also referred to-as limit value signalling devices, eachsuch device having'aninput 13 and two outputs 14 and 15. The out-put 14 supplies a signal when the input 13 has positive polarity,- and the output 15 supplies a signal whenthe input-13hasnegative polarity. The null amplifier II is energized' by a voltage which is proportional to-the fault current i, andthe null amplifier 12 is energized by a voltage which is proportional to the temporal derivation di/ d1. Both voltages can readily. be obtained at the two components Rb, E of the comparison impedance.

Each. output 14 and 15 is extended: to an And gate indicated respectively at ldand 17. Each A-nd gate has two inputs18, 1'9 and anoutput 2t), the-latter supplying a signal only when. both inputs 18, 19. are supplied with a signal. Accordingly, theoutput of the And-gate 16 carries a signal so long as: i and di/dtrare positive, and the output of the And-gate 17 carries: a signal so long asi and di/dt are negative. The two And-gatesrlfi: and 17 trigger the operation. of a relay or switch 21' which is provided with two. windings, and also a memory stage 22, also marked M for memory,,such. stage. 'consistinglfor example, of asimple bistablev fiiprfiop stage and being provided with two inputs 23, 2.4.. and two'outputs 25,-. 2.6. The output 25 supplies a signal responsive; to asignal extended to the input 23, until a signal is extended to the input 24. From this instant on the output 26 will supply a signal until the input 23 is triggered again.

To the integrating stages 27, 28, each comprising a resistor and a capacitor, are conducted the voltages u and Au. So long as the relay 21 is at normal or deenergized, its contacts 29, 30 will be in the illustrated positions, thereby short-circuiting the capacitors by low resistance resistors 31 and 32, allowing integration of the voltages at and Au only during the evaluation time interval t in which i and di/dt have the same sign, since the relay 21 is energized only responsive to such condition. At the end of the evaluation time interval, the capacitors of the integrating members will be short circuited again, and at the respective resistors 31 and 32 will appear a voltage impulse with a polarity corresponding to that of the voltage-time-integral of the corresponding voltage. These two impulses, when positive, are conducted to two respective inputs of the And-gate 33 to the third input of which is connected the output 25 of the memory 22 (M). This And-gate 33 delivers at its output a signal only when the tWo voltage-time integrals from u and Au are at the end of an evaluation interval with positive i and di/dt, likewise positive.

In the event that the impulses are negative, they are over a reversal stage 34 (alsomarked U) changed into positive impulses and conducted to the two inputs of an And-gate 35 having a third input which is connected with the output 26 of the memory 22 (M). This And-gate delivers a signal only when the two voltage-time-integrals of u and AM are at theend of an evaluation interval with negative i and di/dt, likewise negative.

The operation requirement according to the invention is accordingly complied with as soon as one of the two Aud-gates 33 or 35 delivers a signal, and tripping of the involved circuit breaker must take place.

Another embodiment of a high speed distance protection may be constructed based upon the following operation or tripping requirements:

A tripping or operation shall be eifected when the voltage it as well asthe voltage Au have, within an evaluation interval t in which i and di/dt have identical signs, the same si n as i and di/dt at least during a predetermined coincidence time t Based upon a curve form of the current according to Equation 4, there may be derived, for the above stated operation requirements, limits or borders for the operation or tripping region in the impedance diagram, as shown in FIG. 5 for ==wt 60. Straight line flights intersectingrespectively the point of origin and end of the vector Z are again shown in this figure-these flights however exhibiting bends at these two points. The operation region lies again between the straight lines extending through the origin and those extending through the point (R0: 0) I FIG. 6 shows a circuit which delivers a tripping command or signal responsive to compliance with the operation requirements according to FIG. 5 p

The four input voltages which are respectively proportional to i, di/dt, u and Au=z: -u, are conducted to four null amplifiers 61, 62, 63 and 64, having functions corresponding to those of the amplifiers ll and 12 shown in FIG. 4. The outputs of the amplifiers 61 and 62 are, as the outputs of the amplifiers Hand 12 inFlG. 4, connected to And-gates, in the present case And-gates 65 andze, so that the output of the And-gate .65 will deliver a signal so longas i and also di/clt are positive, while the output of the And-gate 66 will deliver a signal when these two values are negative. Accordingly, the signals of these two And-gates again determine the evaluation times separately according to the polarities o f i and di/dt.

The outputs of the two amplifiers63, g64'and those of the And-gates 65, 66 are over further And-gates 67, 68, 69, 7t) mutually linked, so that the And-gates 67 to 70 deliver a signal at the respective output, in the following cases, namely:

And-gate 67: i, di/dt and Au positive; And-gate 68: i, di/dt and Au negative; And-gate 69: z, di/dt and 11 positive; And-gate 70: i, di/dt and u negative.

The outputs of the And-gates 67, 68 and 69, 70, respec tively, are connected with corresponding timing or delay stages 71 and 72, respectively. Theoutput of the respective delay stages delivers a signal when the signal on one of the two inputs persists for an interval exceeding a predetermined duration. Such signal disappears again upon disappearance of the signal of longer duration. Upon making the time constant 1' of the delay stages 71, 72 equal to the coincidence time t the two delay stages will deliver a signal when the coincidence time interval of the corresponding voltage u or Au is, during an evaluation interval, greater than the predetermined coincidence time t The output signals of the two delay stages do not normally appear simultaneously and therefore must be storedin memory stages 73 and 74, respectively, since a tripping operation must be effected only when both voltages 1: and Au reach the predetermined coincidence time t during theevaluation interval. These memory stages 73, '74 are sodesigned that they deliver an output signal as soon as the inputs are triggered which are connected to the delay stages. The output signal disappears only when the other input of the memory stage receives a signal.v This cancellation or extinguishing signal is supplied by a differentiating stage 75 always at the start of a new evaluation period, so that the memory stages begin each new evaluation period without an output signal.

The outputs of the two memory stages are connected to the And-gate 76. This And-gate issues the tripping command or signal responsive to an output signal at both memory stages '73, 74, that is, when both volt-ages u and Au had, during the preceding evaluation time t the same same sign as i and di/dt for a longer interval than the predetermined coincidence time t;;.

FIGS. 3 and 5 show that the release regions of the described protection systems cannot yet be fully well adapted to the requirements of an impedence distance protection. Moreover, they have the peculiarity that there appears at offset fault current an alternation of the tripping region, resulting especially in the embodiment accordingto FIGS. 5 and 6, in a considerable extension or widening of the operation region. The reason resides in thatthe specified operation requirement can be easier complied with in the case of half waves longer than A futher improvement of the electronic distance protection can be eifected in accordance with the following basic thoughts of the present invention:

While theprotective systems known until now operated I so that a tripping command or signal was issued only upon compliance with a predetermined operation requtrernent, the example of an embodiment of a distance protection to be now described operates so that a tripping command is issued at the end of each evaluation period, such command being, however, blocked upon compliance with a predetermined blocking requirement. Likewise the tripping requirement was easier complied with in the case of current half waves greater than 180, now it applies with respect to the blocking requirement. The

region or range in which the blocking requirement appears is then likewise extended, with the feature, how- .ever', that the tripping region is reduced at current waves greater than 180.

There is, however, the danger that a necessary block ing requirement. is suppressed at currenthalf waves smaller than 180. In order to overcome this drawback, g there is specified a-given length of the evaluation time, p

7 before the release signal can be given, thereby excluding the harmful short current half Waves.

The corresponding example of an embodiment of a high speed distance protection system according to the present invention therefore operates in accordance with the following principle:

At the end of each evaluation period which is given by the time t during which i and di/dt have the same sign, that is, at the current maximum, is delivered a tripping signal, when this evaluation period exceeds a predetermined time t (t-g, t The tripping signal is further blocked only when either the line voltage a or the difference voltage Au=u -u had, at some point of the same evaluation period, another sign that i and di/dt for an interval longer than a predetermined time 1 FIG; 7 shows the borders or limits of the tripping region of such a protective system according to the current course explained with reference to Equation 4. The times and are thereby so selected that, with w as the circuit frequency of the electrical network magnitudes, p =wt =70 and" p =wf :10. The vector of the comparison impedance is again represented by Z (R (0L0). It will be seen that the tripping region embraces very closely a rectangle with the comparison impedance as a diagonal (corresponding to the regionb in FIG. 2). The scattering for various values of the angle or; is particularly for the important horizontal delimiting noticeably small. Angles o (qo 90) need not be considered since the evaluation time t is in such cases shorter than the specified time t The inclination of the horizontal delimitation with respect to the horizontal is in first approximation given by the angle The shorter the time t is made, the better will the tripping region be matched to the rectangle and the smaller will be the changes of the tripping region in the case of oitset currents. The rectangle as an operation region exactly obtained for t =0. However, such a protection arrangement would have the drawback that any short interference pulse occurring during the evaluation period could result in blocking the tripping operation. It is therefore advantageous to select t as small as possible and yet, always large enough so that interference pulses of normal duration do not adversely affect the operationof the protective system. A reasonable range of valuesis, for example, 0.2 ms. t 0.6 ms.

Itis thereby. possible to determine a closely delimited practically rectangular shaped tripping region in the impedance diagram, which is hardly affected by offset currents. The requirements of the protective relaying technique are particularly well satisfied when the inductanceof the comparison impedance is made about equal to 85 percent of the inductance of the line section to be protected and considering in the ohmic resistance of the comparison impedance the resistance of the-line section to be. protected, including the. highest are resistance that may be expected.

FIG. 8 shows as an example anembodiment of a high speed distance protective relaying system operating in accordance with the above noted requirements.-

.to the endof the evaluation period: The differentiating circuit 88 produces an impulse at itsoutput upon disappearance of its input signal, that is, at the end of theevaluation. period and therewith at the current maximum.

The And-gates 89, 9t 91, 92 check the polarities of The 1 four inputvoltages which are respectively proportional to the voltages u and Au during the evaluation period. A signal is thereby produced by the And-gates as follows:

The time delay circuit 93, having four Or-inputs to which are connected these And-gates, now checks whether one of the blocking signals delivered by one of i the Andgates has a duration exceeding the predetermined time t thereby excluding brief interference pulses. As soon as this time is exceeded by a blocking signal, the memory stage 94- will be triggered; This memory stage 94 is circuited so that the signal at its output disappears when the memory stage is triggered from the time delay circuit 93. The signal at its output reappears only when a signal is conducted to the-other input of the memory stage 94. This signal is at the start of each evaluation period producedby the difierentiating circuit 95, thereby effecting at the start of each new evalution period cancellation or extinguishing of a blocking command that may be present from-the preceding evaluation period.

The outputs of the differentiating circuit 88 and of the memory stage 9 4 are conducted to the And-gate 96. This And-gate passes the tripping signal produced by the differentiating circuit 88 only when there is a signal also at its other input. However, this is the case only when no blocking condition had been satisfied in the preceding evalution period, and the tripping impulse is produced only when the evaluation time t is longer than t A high speed distance relaying system according to the circuit shown in FIG. 8 thus-operates exactly according to the requirements of the operation region shownin FIG. 7.

It is thus possible to construct in accordance with the invention a high speed distance relaying'circuit arrangement which has in the RX diagram an ideal tripping region for distance relaying purposes, which is insensitive to short interference pulses, designed only with static components, and which'ir'rthe' case'of a' fault transmits" the tripping impulse to the involved" circuit breaker already in the maximum of the first fully developed half wave of the fault'current.

The application of the circuit described for a single phase line, to a three phase line system is readily accomplished by utilizing in known manner in the place of the line voltage the voltage between two phases or delta voltages and in place ofthe current the diiierence of the two phase currents or delta currents.

Changesmay'be made within the scope andspiritof the appended claims which define what isbelieved to be new and desiredto' have protected by Iietters Patent.

We claim:

1. For use in 'protecting'power' systems in the event of trouble arising along a" line section, a distance relaying circuit arrangement cooperatively associated with a line section'to be protected, said circuit" arrangement responding quickly-to a fault arising along the respective line section for the purpose'o'fforming a criterion for the'operative tripping of a power control'device, means for conducting to' said circuit arrangement the voltage (u) at the line section and the voltage (n at acomparison impedance; means for forming the difference voltage ('Au==u -u), and means'for evaluating in each'current half wave thepolarities-of said voltages or values derived therefrom only during atime interval in which the fault current (i) and its temporal derivation (di/dt) have the identical sign.

2. A circuit arrangement according to claim 1, wherein a't'rippingsi'gnal is 'deliver'edwhen the time integral of the voltage (u) as well as the time integral of the dit- --ference voltage (AM) have. at the end of the evaluation interval (t the same polarity as the fault current (i).

3'. A circuit'arrangeinent according to claim' 1, wherein a tripping signal is delivered when the voltage (a) at the 9 line section as Well as the difference voltage (Au) have, during the evaluation interval, for a predetermined time (1 the same polarity as the fault current (i).

4 A circuit arrangement according to claim 1, wherein the delivery of the tripping signal, at the end of the evaluation interval is omitted only when either or both the voltage (u) or the difference voltage (Au) have at some point of the evaluation interval (t a sign differing from that of the fault current (i).

5. A circuit arrangement according to claim 4, wherein the delivery of a tripping signal is omitted only when either or both the voltage (u) at the line section or the difference voltage (Au) have at some point of the evalua- 19 tion interval at least for a predetermined time a sign differing from that of the fault current (i).

6. A circuit arrangement according to claim 4, wherein the evaluation interval (t embraces the entire time interval during which the loop current (i) and its temporal derivation (di/rlt) have identical signs.

7. A circuit arrangement according to claim 4, wherein the tripping signal is delivered only when the evaluation interval (t is greater than a predetermined time interval (t which corresponds at least to /8 cycle referred to the network frequency.

No references cited. 

1. FOR USE IN PROTECTING POWER SYSTEMS IN THE EVENT OF TROUBLE ARISING ALONG A LINE SECTION, A DISTANCE RELAYING CIRCUIT ARRANGEMENT COOPERATIVELY ASSOCIATED WITH A LINE SECTION TO BE PROTECTED, SAID CIRCUIT ARRANGEMENT RESPONDING QUICKLY TO A FAULT ARISING ALONG THE RESPECTIVE LINE SECTION FOR THE PURPOSE OF FORMING A CRITERION FOR THE OPERATIVE TRIPPING OF A POWER CONTROL DEVICE, MEANS FOR CONDUCTING TO SAID CIRCUIT ARRANGEMENT THE VOLTAGE (U) AT THE LINE SECTION AND THE VOLTAGE (UO) AT A COMPARISON IMPEDANCE, MEANS FOR FORMING THE DIFFERENCE VOLTAGE ($U=UO-U), AND MEANS FOR EVALUATING IN EACH CURRENT HALF WAVE THE POLARITIES OF SAID VOLTAGES OR VALUES DERIVED THEREFROM ONLY DURING A TIME INTERVAL IN WHICH THE FAULT CURRENT (I) AND ITS TEMPORAL DERIVATION (DI/DT) HAVE THE IDENTICAL SIGN. 